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CS1600 Low-cost PFC Controller for Electronic Ballasts
Features & Description
Lowest PFC System Cost for Electronic Ballasts Variable Frequency Discontinuous Conduction Mode Improved Efficiency Due to Variable Switching Frequency EMI Signature Reduction from Digital Noise Shaping Integrated Feedback Compensation Overvoltage Protection with Hysteresis Overpower Protection with Shutdown UVLO with Wide Hysteresis Thermal Shutdown with Hysteresis
Description
CS1600 is a high-performance Variable Frequency Discontinuous Conduction Mode (VF - DCM), active Power Factor Correction (PFC) controller, optimized to deliver the lowest PFC system cost for electronic ballast applications. A variable ON time / variable frequency algorithm is used to achieve near unity power factor. This algorithm spreads the EMI frequency spectrum, which reduces the conducted EMI filtering requirements. The feedback loop is closed through an integrated compensation network within the IC, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, overpower, open- and short-circuit protection, overtemperature, and brownout help protect the device during abnormal transient conditions.
Pin Assignments
NC STBY IAC FB 1 2 3 4 8 7 6 5 NC VDD GD GND
8-lead SOIC
D5 L1 RAC D6 RFB
R1a BR1 BR1 R1b
R2a
CS1600
1 NC IAC VDD NC STBY FB GD GND 2
R2b C3a Clink R2c 4 C3b 6 5 R3 Q1
AC Mains
C1
R1c 3
+12V
7 C2 8
BR1
BR1
Advance Product Information
Cirrus Logic, Inc. http://www.cirrus.com
This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved)
JUL `10 DS904A7
CS1600
1. PIN DESCRIPTIONS
NC STBY IAC FB 1 2 3 4 8 7 6 5 NC VDD GD GND
Table 1. Pin Descriptions Pin Name NC Pin # I/O Description No Connect -- Connect these pins to VDD to prevent any leakage path that could arise from leaving them unterminated. Standby -- This is an active-low pin. Shorting this pin to GND disables PFC switching. The input has a pull-up resistor and should be driven with an open-collector device. Leave this pin unterminated when not in use. Rectified Line Voltage Sense -- The IAC pin is used to sense the rectified line voltage. This signal, in conjunction with the signal on the FB pin, is used in the Power Factor Correction (PFC) algorithm A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. Feedback Voltage Sense -- The FB pin is used to sense the output voltage of the PFC stage. This signal, in conjunction with the signal on the IAC pin, is used in the Power Factor Correction (PFC) algorithm. A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. Ground -- GND is a common reference for all the functional blocks in this device. Gate Drive -- GD is the output of the device with a source capability of 0.5 A and a current sink capacity of 1 A. IC Supply Voltage -- VDD is the input used to provide bias to the device. This pin has an internal shunt to ground. An external bias needs to be applied for steadystate operation. A low-ESR ceramic decoupling capacitor at this pin is recommended for reliable operation of this device.
1, 8
-
STBY
2
IN
IAC
3
IN
FB
4
IN
GND GD
5 6
- OUT
VDD
7
IN
2
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CS1600
2. CHARACTERISTICS AND SPECIFICATIONS
2.1 Absolute Maximum Ratings
Pin 7 2,3,4 3,4 6 6 1,2,3,4,5,6,8 1,2,3,4,5,6,8 1,2,3,4,5,6,8 2. Symbol VDD VIN IIN VGD IGD ESD ESD ESD PD TJ TStg IC Supply Voltage1 Parameter Value Vz -0.5 to VDD 50 -0.3 to VDD -1.0 / +0.5 2000 200 500 600 -40 to +125 -65 to +150 Unit V V mA V A V V V mW C C
Input Voltage Input Current Gate Drive Voltage Gate Drive Current Human Body Model Machine Model Charged Device Model Total Power Dissipation at 50 C2 Junction Temperature Operating Range Storage Temperature Range
Notes: 1. The CS1600 has an internal shunt regulator that controls the nominal operating voltage on the VDD pin.
Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50 mW / C for variation over temperature.
2.2
Electrical Characteristics
Recommended operating conditions (unless otherwise specified): TA = TJ = -40 to +125 C, VDD = 10 to 15 V, GND = 0 V. Typical values are at TA = 25 C. Parameter VDD Supply Voltage VDD Turn-on Threshold Voltage VDD Turn-off Threshold Voltage UVLO Hysteresis Zener Voltage Supply Current Section Start-up Supply Current Standby Supply Current Operating Supply Current PFC Gate Drive Section Maximum Operating Frequency3,4 Minimum Operating Frequency3,4 Minimum Duty Cycle Maximum Duty Cycle3,4 Minimum On Time Output Source Resistance Output Sink Resistance Rise Time Normal mode, VDD = 13 V Normal mode, VDD = 13 V VDD = 13 V, STBY < 0.8 V VDD = 13 V VDD = 13 V IGD = 100 mA, VDD = 13 V IGD = -200 mA, VDD = 13 V CL = 1 nF, VDD = 13 V fSW(max) fSW(min) tDC_min Dmax ton_min ROH ROL tr 62 20 64 0.45 66 22 66 0.5 9 6 32 70 23 0 68 0.55 60 kHz kHz % % s ns VDD < Vth(St) STBY < 0.8V CL = 1nF, fsw(max) = 70 kHz IST ISB IDD 68 80 1.7 80 112 1.9 A A mA IDD = 20 mA VDD increasing VDD decreasing Vth(St) Vth(Stp) VHys VZ 8.4 7.1 17.0 8.8 7.4 1.3 17.9 9.3 7.9 18.5 V V V V Condition Symbol Min Typ Max Unit
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CS1600
Parameter Fall Time Output Voltage Low Output Voltage High Feedback and Protection 3, 7 Reference Current Overvoltage Protection Threshold Recovery from Overvoltage Protection Start-up Mode Start Threshold Normal Mode Start Threshold Recovery from Undervoltage Overpower Protection Threshold 4 Overpower Protection Hysteresis 4 Input Brownout Protection Threshold Input Brownout Recovery Threshold Thermal Protection Thermal Shutdown Threshold 3 Thermal Shutdown Hysteresis STBY Input Logic Threshold 5 Low High
Condition CL = 1 nF, VDD = 13 V IGD = -200 mA,VDD = 13 V IGD = 100 mA,VDD = 13 V
Symbol tf VOL VOH
Min 11.3
Typ 15 0.9 11.8
Max 30 1.3 -
Unit ns v v
25 C -40 to +125 C 25 C -40 to +125 C 25 C -40 to +125 C 25 C 25 C 25 C GDRV turns off, 25 C % of full load as defined by Eq. 3 Vout = 460V, GDRV turns off, 25 C Vout = 460V, GDRV turns on, 25 C
Iref
125 120 104 101 98 94 83 97 123 -
129 108 101 85 99 10 125 5 85 97
135 136 111 113 105 105 87 101 127 93 104
A % % % % % % Vrms Vrms
VBP(th) VBR TSD TSD(Hy)
79 91
130 -
143 9
155 -
C C
VDD - 0.8
-
0.8 -
V
2.3
Thermal Characteristics
Parameter Thermal Resistance (Junction to Ambient)6. Thermal Resistance (Junction to Case)6. 3. 4. 5. 6. 7. Value 159 39 Unit C / W C / W
Symbol RJA RJC
Specifications guaranteed by design & characterization. Specifications measured as an instantaneous quantity NOT as a time-averaged quantity. STBY is designed to be driven by an open-collector device. The input is internally pulled up with a 600 k resistor. The package thermal impedance is calculated in accordance with JESD 51. Based upon input voltage 120 to 277 VAC and an output voltage (Vout) of 460 V, with boost inductance of 380 H, output capacitance of 23.5 F, and VDD of 13 V.
4
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3. TYPICAL ELECTRICAL PERFORMANCE
3.5 3 2.5 CL = 1 nF fSW(max) = 70 kHz TA = 25 C
11 13
12
IDD (mA)
2
1.5 1 0.5 Falling 0 0 2 4 6 8 10 12 14 16 18 20 Rising
VDD (V)
10
9
Startup
8
UVLO
7 -50
0
Figure 1. UVLO Characteristics
VDD (V)
TEMP (o C)
50
100
150
Figure 2. Start-up & UVLO vs. Temperature
2
19 IDD = 20 mA
UVLO Hysteresis (V)
1.5
18.5
1
VZ (V)
-50 0 50 100 150
18
0.5
17.5
0
17
TEMP ( o C)
-50
0
50
100
150
TEMP ( oC)
Figure 3. UVLO Hysteresis vs. Temperature
Figure 4. VDD Zener Voltage vs. Temperature
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CS1600
1.8 Operating 1.6
14 12
Supply Current (mA)
1.4 1.2 1.0 0.8 0.6
Zout (Ohm)
VDD = 13 V CL = 1 nF fSW(max) = 70 kHz
Source 10 8 6 Sink 4
0.4 0.2
2
Start-up
Standby
VDD = 13 V Isource = 100 mA Isink = 200 mA
Standby
Start-up
0 -50
0
TEMP ( o C)
50
100
150
0 -60
-40
Gate Resistor (ROH, ROL) Temp (oC)
-20
0
20
40
60
80
100
120
140
Figure 5. Supply Current (ISB, IST, IDD) vs. Temperature
Figure 6. Gate Resistance (ROH, ROL) vs. Temperature
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4. INTRODUCTION
The CS1600 is a digitally controlled Power Factor Correction (PFC) controller that operates in the Variable Frequency Discontinuous Conduction Mode (VF - DCM). The CS1600 uses a proprietary digital algorithm to optimize control of the power switch to deliver highly efficient performance for electronic ballast applications. With this control scheme, the total number of external components needed is minimized in comparison to conventional control techniques, thus reducing the overall system cost. Digital control is achieved by constantly monitoring two voltages - the PFC output voltage (Vlink) at pin FB and the rectified AC line voltage (Vrect) at pin IAC. This is done by measuring the currents that flow into the respective pins. These currents are then fed to the inputs of two analog-to-digital converters (ADCs) and are compared against an internal target current, Iref. The digital outputs of the two ADCs are then processed in a control algorithm which determines the behavior of the CS1600 during start-up, normal operation, and under fault conditions such as brownout, overvoltage, overcurrent, overpower, and over-temperature. Details of operation during these conditions are discussed in later sections of this document. Some of the key features of the CS1600 are as follows: * Discontinuous Conduction Mode with Continuously Variable Switching Frequency The PFC switching frequency is varied every switching cycle. This allows for a spread spectrum which minimizes the conducted EMI peaks at any given frequency, thereby minimizing the size and cost of the EMI filter required at the front-end. During start-up, the control algorithm limits the maximum ON time and adjusts the frequency to avoid inductor saturation and provides a near-trapezoidal envelope for the input current during every half cycle. During normal operation, as the line voltage changes over half of a line cycle, the frequency varies approximately 2:1 as shown in Figure 7 below.
120
Switching Frequency (% of Max)
100
80
% of Max
60
Line Voltage (% of Max)
40
20
0
0
45
90
135
180
Rectified Line Voltage Phase (Deg.)
Figure 7. Switching Frequency vs. Phase Angle Maximum power transfer occurs at the peak of the AC line voltage, at which time, the frequency reaches its maximum value. Switching losses are minimized during periods of low power transfer by switching at lower frequencies near the zero-crossing of the AC line. This switching frequency profile helps reduce total BOM cost through savings in the size of the boost inductor and the EMI filter components, while at the same time, improving overall system efficiency. * Integrated Feedback Control No external feedback compensation components are required for the CS1600. The internal digital control engine self-compensates the feedback error signal using an adaptive control algorithm. * Protection Features The CS1600 provides various protection features such as undervoltage, overcurrent, overpower, open and short circuit protection and brownout. It also provides the user with the option of using the STBY pin to disable switching of the device.
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CS1600
4.1 PFC Implementation
CRM mode near the peaks of the input line, in order to enable maximum power delivery, as illustrated in Figure 10 below.
The PFC switching frequency profile over the line period has been discussed in detail in Section 4. In addition, the digital control algorithm tracks changes the AC input and operates in different frequency bands at different line voltages as illustrated in Figure 8 and Figure 9 below.
DCM
Quasi CRM
DCM
Quasi CRM
DCM ILB
fSW [kHz]
100 Burst Mode 70 Max fSW
Figure 10. DCM and quasi-CRM Operation with CS1600
4.1.1
35 Min fSW
Start-up Mode vs. Normal Mode
CS1600 operates in two discrete states: Start-up mode: When the output voltage of the PFC stage, Vlink, is <90% of its nominal value, the device operates in the start-up mode. It continues operating in this mode till the nominal Vlink voltage is reached. The start-up algorithm provides an ON time which is varied in proportion to the sensed rectified voltage, while changing the switching frequency to provide maximum power. During this start-up phase of operation, the switching frequency could be significantly lower than the normal operating frequency, and the input current waveform is forced into following a trapezoidal envelope in phase with the line voltage, to maximize energy transfer. The ON time and the switching frequency of the IC ensure that peak currents are kept controlled to prevent saturation of the boost inductor during this period. Normal mode:
Min fSW
5%
50%
100%
PO [W]
Figure 8. Switching Frequency vs. Output Power Vin < 165 VAC
fSW [kHz]
60 48 Burst Mode Max fSW
24
5%
50%
100%
PO [W]
Figure 9. Switching Frequency vs. Output Power Vin > 165 VAC The CS1600 primarily operates in the DCM mode with a properly sized inductor. However, it will move into a quasi-
Once Vlink reaches its nominal value, the chip operates in the normal mode. Here, the frequency follows the profile shown in Figure 7, and the ON time is varied to achieve PFC. Any drop in Vlink to below its undervoltage threshold, as defined in Section 2.2. Electrical Characteristics re-triggers the start-up mode of operation. A simplified illustration of operation in these two modes is shown below in Figure 11.
100% Startup Mode Startup Mode 90%
Normal Mode
Normal Mode
t [ms]
Figure 11. Start-up and Normal Modes
8
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CS1600
4.1.2 Burst Mode
Iref = Target Reference current used for feedback
In addition to the start-up mode and normal mode of operation, the controller enters the burst mode of operation when the estimated output power (PO) is < 5% of its nominal value. During this stage, the PFC driver is disabled intermittently over a full line cycle period, as shown in Figure 12. The period of time for which the PFC drive is disabled depends on the level of loading present..
PO [W]
Vlink
IFB
RFB
VDD 7
RIFB 15k
FB 4
ADC
5% Burst Mode Active t [ms] Vin [V] Vin PFC Disable
IFB
Figure 13. Output Feedback
Vlink
RFB
VDD 7
FET Vgs
RIFB 15k
ADC
t [ms]
FB
4
Figure 12. Burst Mode of Operation
4.2
Input Feedforward and Output Regulation 4.3
4.3.1
Figure 14. Input Feedforward
The CS1600 continuously monitors the rectified AC line and the PFC output voltage through sense resistors tied to the IAC and the FB pins to monitor the voltages, scaled as currents. The rectified AC line sense resistor RAC needs to be the same size of the resistor RFB used for current feedback from the PFC output voltage. These currents are effectively compared against an internal reference current to provide adaptive PFC control. The resistor values are calculated as follows: V link - V DD R FB = ---------------------------I ref R AC = R FB where RFB = Feedback resistor used to sense the PFC output voltage RAC = Feedforward resistor used to sense the rectified line voltage Vlink= PFC Output Voltage VDD = IC Supply Voltage [Eq.1]
Protection Features
Overvoltage Protection
If the PFC output voltage, Vlink, exceeds the overvoltage threshold, as scaled by the current monitored by the sense resistors, the CS1600 provides protection by disabling the gate drive. A nominal hysteresis is provided to allow the system to recover from the fault condition, before switching is resumed.
4.3.2
Overcurrent Protection
The CS1600's digital controller algorithm limits the ON time of the Power MOSFET by the following equation: [Eq.2] 0.001126 T on -----------------------V rect Where Ton is the max time that the power MOSFET is turned on and Vrect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appropriately. For this type of line disturbance, additional protection mechanisms, such as fusible resistors, fast-blow fuses, or other current-limiting devices, are recommended.
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CS1600
4.3.3 Overpower Protection
for the output voltage, drops to 49% of its nominal value. Detection of brownout for a period of 56 ms disables the gate drive. The device continues to monitor the input voltage while in this condition. The CS1600 exits the brownout mode when the input current scales up to, and stays above 56.4% of its nominal value for a period of 56 ms. To minimize false detects, the brownout detection circuit increases the brownout detection time by a factor of 1.6 mS/V for every volt differential between the minimum operating voltage and the brownout threshold, following half of a line cycle of exceeding the brownout threshold. The following diagram illustrates the brownout sequence whereby the CS1600 enters standby, and upon recovery from brownout, enters normal operation..
TBrownout Brownout Thresholds Upper Lower Start Timer 56 ms 56 ms
The nominal output power is estimated internally by the CS1600 from the following equation
2 V link - ( V in ( min ) x 2 ) P = x x ( V in ( min ) ) x -------------------------------------------------------o 2 x f max x L B x V link
[Eq.3]
where Po = rated output power of the system = efficiency of the boost converter = estimated as 100% by the internal PFC algorithm Vin(min) = minimum RMS line voltage for operation Vlink = PFC output voltage fmax = maximum switching frequency LB = boost inductor used in the application V link V link - ------------- x 90V x 2 V link 400V 90V = ------------- x ------------------- x ------------------------------------------------------------------- 400V V in ( min ) V link - V in ( min ) x 2
2
Operation estimated to be at power levels higher than that calculated by Eq. 3 above is tracked by the IC as an overpower condition. During this phase, the PFC output voltage, Vlink, is reduced and will continue to decrease as the power draw increases. When Vlink reaches its undervoltage threshold, it goes into the start-up mode as explained in section 4.1.1. At this point, the overpower protection timer is activated. If this condition continues to exist for 112 ms, the gate drive is disabled for a period of about 3 seconds. This "hiccup" mode of operation continues until the fault is removed. If a value of the boost inductor other than that obtained from Eq. 3 above is used, the total output power capability as well as the thresholds for the different operating conditions will scale accordingly.
Enter Standby Start Timer
Exit Standby
Figure 15. Brownout
4.3.6
Over-temperature Protection
Over-temperature protection is activated and PFC switching is disabled when the die temperature of the device exceeds 125C. There is a hysteresis of about 30C before resumption of normal operation.
4.4
Standby (STBY) Function
4.3.4
Open/short circuit protection
The standby (STBY) pin may be used as a means to force the CS1600 into a non-operating, low-power state. The STBY input should be driven by an open-collector/open-drain device. Internal to the pin, there is a pull-up resistor connected to the VDD pin as shown in Figure 16. A filter capacitance of about 1000 pF is recommended while this pin is being used.
CAP
The CS1600 protects the system in case the feedforward resistor tied to the IAC pin or the feedback resistor tied to the FB pin is open or shorted to ground. A fault seen on the resistor going into the FB pin would imply no current being fed into the pin, which would trigger the Vlink undervoltage algorithm as described in Section 4.3.1. A fault detected on the IAC pin would trigger the brownout condition discussed in Section 4.3.5 below.
STBY
600 k
CS1600 <1 nF See Text GND
4.3.5
Brownout Protection
Brownout occurs when the current representing the rectified input voltage, nominally 100% of the reference current used
Figure 16. STBY Pin Connection
10
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CS1600
5. FLUORESCENT BALLAST APPLICATION EXAMPLE
The following section gives an example for a front-end PFC stage design for an electronic ballast application. The equations that follow may be used as guidelines for any other requirements using the CS1600.
D5 L1 RAC D6 RFB
R1a BR1 BR1 R1b
R2a
CS1600
1 NC IAC VDD NC STBY FB GD GND 2
R2b C3a Clink R2c 4 C3b 6 5 R3 Q1
AC Mains
C1
R1c 3
+12V
7 C2 8
BR1
BR1
Figure 17. CS1600 Basic Application Circuit
5.1
Component Selection Guidelines
R AC = R FB R AC = 3.45M where [Eq.5]
The following design example is for a wide-input-voltage fluorescent ballast application using 2 T5 lamps in series for a total nominal power of 108W.The target specifications for the PFC portion of the design, assuming a 94% efficient second stage, are as follows:
Vin(min) Vin(max) Vlink Po
108 VAC 305 VAC 460 V 115 W 95%
RFB = Feedback resistor used to reflect the PFC output voltage RAC = Feedforward resistor used to reflect the rectified line voltage Vlink= PFC Output Voltage VDD = IC Supply Voltage Iref = Target reference current used for feedback 1% or lower tolerance resistors are recommended to maximize the tightly toleranced system behavior provided by the unique digital controller in the CS1600. Resistors may be separated into two or more series elements if voltage breakdown and/or regulatory compliance is of concern.
5.1.1
IAC and IFB Sense Resistors
The rectified line voltage, VAC, and the output voltage of the PFC boost converter, Vlink, are scaled as currents by using sense resistors, whose values are estimated based on the equations below: V link - V dd [Eq.4] R FB = --------------------------I ref 460 - 12 R FB = ---------------------------6 130 x 10 R FB = 3.45M
5.1.2
PFC Input Filter Capacitor
For a typical 115 W PFC output stage required to power up a 108 W fluorescent ballast, an input filter capacitance of 0.33 F is recommended. Capacitor tolerances and the value of the EMI filter capacitor need to be considered when selecting the value of the capacitor to be used in this application.
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CS1600
5.1.3 PFC Boost Inductor
The minimum RMS current rating, IFET(rms), required for the FET is calculated as follows: PO [Eq.9] I FET ( rms ) = ----------------------------V in ( min ) x 115 I LB ( rms ) = --------------------------108 x 0.95 I LB ( rms ) = 1.12A
Equation 3 can be rewritten to calculate the PFC boost Inductor, LB, as follows: V link 2 V link - ------------- x 90V x 2 V link 400V 90V ------------- x ------------------- x -------------------------------------------------------------------- [Eq.6] = 400V V in ( min ) V link - V in ( min ) x 2 V link V link - ------------- x 90V x 2 V link 400V 90V - 2 -------------------------------------------------------------------- = 0.937 = ------------- x ------------------- x 400V V in ( min ) V in ( min ) x 2 - V
link 2 V link - ( V in ( min ) x 2 ) L B = x x ( V in ( min ) ) x -------------------------------------------------------2 x f max x P O x V link
5.1.5
PFC Diode
The PFC diode peak current is equal to the inductor peak current: [Eq.6] I D ( pk ) = I LB ( pk ) I D ( pk ) = 3.17 A The PFC diode average current is calculated as follows: PO I D ( avg ) = ----------V link 115 I D ( avg ) = --------460 I D ( avg ) = 0.25 A [Eq.11] [Eq.10]
2 ( 460 - 108 x 2 ) L B = 0.937 x 0.95x 108 x --------------------------------------------------------------- = 431H 3 2 x 70 x 10 x 115 x 460
The RMS current rating for the inductor can be estimated as follows: PO I LB ( rms ) = ----------------------------V in ( min ) x I LB ( rms ) 115 = --------------------------108 x 0.95
[Eq.7]
5.1.6
I LB ( rms ) = 1.12A The peak inductor current, ILB(pk), may be estimated using the following equation: 4 x PO I LB ( pk ) = ------------------------------------------ x V in ( min ) x 2 I LB ( pk ) 4 x 115 = ----------------------------------------0.95 x 108 x 2
PFC Output Capacitor
The output capacitor needs to be designed to meet the voltage ripple and hold-up time requirements. In the case of a costsensitive ballast application, the hold-up requirement is not a key requirement. The CS1600 has been designed to operate with a low output capacitance of approximately 0.2 F per watt of output power. For this specific application: 0.2F C out = --------------- x 115W = 23F W The 120 Hz ripple on the output capacitor may be estimated using the following equation: PO V link ( rip ) = ----------------------------------------------------------------------2 x f line ( min ) x V link x C out 115 = -----------------------------------------------2 x 45 x 460 x 23 = 40.2V where Cout = Output Capacitance value Po = Output Power fline(min) = Minimum Line Frequency Vlink = PFC Output Voltage Vlink = Peak-Peak Voltage Ripple on the PFC Output [Eq.12]
[Eq.8]
I LB ( pk ) = 3.17 A Inductor tolerances should be considered when estimating the peak currents present in the application. The internal control algorithm of the controller dictates that the peak inductor current seen in the application could be as high as a pre-defined threshold of 0.001984 times the inverse of the inductor, which in this example amounts to 4.72 A. Care needs to be taken to ensure that the saturation current rating of the PFC boost inductor factors in this threshold used for the protection schemes.
5.1.4
PFC MOSFET
The peak voltage stress on the PFC MOSFET is a diode drop above the output voltage. Accounting for leakage spikes, for the 460 V output application, a 600 V FET is recommended. The FET should be able to handle the same peak current as that seen through the inductor. This would amount to 3.17 A.
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The voltage rating on the capacitor needs to account for the operation of the device before it hits the overvoltage protection threshold. This is typically 105% of nominal value, which is 483 V. With the ripple voltage factored in, 22 F of capacitance rated at 500 V would suffice for this application.
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CS1600
5.2 Bill of Materials (for Application Example shown in Figure 17)
Designator R1a R1b R1c R2a R2b R2c R3 C1 C2 C3a C3b BR1 D5 D6 L1 Q1 CS1600 Value 1.5 M 1.5 M 1.5 M 1.5 M 1.5 M 1.5 M 24.9 0.47F 4.7F 23.5F 4A, 600V 1 A, 600 3A, 600V 420H (max) 9A, 600V 2 47F, 250V caps in series Bridge diode - GBU4J-BP 1N4005 MURS360 Premier Magnetics TSD-2798 Renco RLCS-1002 FCP9N60N CS1600-FSZ Description/Part Number
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5.3
Eq. # 1, 4
Summary of Equations
Equation
V link - V DD R FB = ---------------------------I ref
2, 5
R AC = R FB
3, 6
2 V link - ( V in ( min ) x 2 ) P O = x x ( V in ( min ) ) x -------------------------------------------------------2 x f max x L B x V link
7
PO I LB ( rms ) = ----------------------------V in ( min ) x
8
4 x PO I LB ( pk ) = ------------------------------------------ x V in ( min ) x 2
9
PO I FET ( rms ) = ----------------------------V in ( min ) x
10
I D ( pk ) = I LB ( pk )
11
PO I D ( avg ) = ----------V link
12
PO C out = -------------------------------------------------------------------------------------2 x f line ( min ) x V link x V link ( rip )
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CS1600
6. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8 JEDEC # : MS-012
MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8
16
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7. ORDERING INFORMATION
Part # CS1600-FSZ Temperature Range -40 C to +125 C Package Description 8-lead SOIC, Lead (Pb) Free
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number CS1600-FSZ Peak Reflow Temp 260 C MSL Ratinga 2 Max Floor Lifeb 365 Days
a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30 C, 60% relative humidity.
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CS1600
9. REVISION HISTORY
Revision A1 A2 Date OCT 2009 MAR 2010 Changes Initial Advance Information release. Revised feature list, product description and parametric table to reflect the C0 version of silicon. Revised to reflect the update in switching frequency and variation of frequency over line. Revised parametric table and equations to reflect the C1 version of silicon. Updated with additional test bench data for EP level. Added RJA and RJC in electrical specifications section. Updated operating supply current, overpower protection recovery, output capacitance calculation. Added Figure 6.
A3
MAR 2010
A4
APR 2010
A5 A6 A7
MAY 2010 JUN 2010 JUL 2010
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL CORE, and the EXL CORE logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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DS904A7

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Price & Availability of CS16001007

	To Download CS16001007 Datasheet File
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